Enhanced FPGA-Based Controller for Three Phase Shunt Active Power Filter
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1
Department of Electronics, University of M’Sila, M’Sila, Algeria
2
Department of Electronics, Ferhat Abbas Setif1 University, Setif, Algeria
Power Electronics and Drives 2023;8 (43):128-141
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ABSTRACT
In this paper, a three-phase shunt active power filter (SAPF) controller with a fully digital implementation is presented. The main goal
of this contribution is to implement a digital direct power control (DDPC) algorithm without phase-locked-loop (PLL) for SAPF. This
algorithm is intended for power quality improvement and current harmonic elimination. The controller introduced in this paper is cost-
effective, has a fast-dynamic response, and has a simple hardware implementation. In order to comply with the above specifications,
a dedicated controller has been conceived and fully implemented within a field-programmable gate array (FPGA) device. This
FPGA-based controller integrates the whole signal-processing functions needed to drive the SAPF, as well as an original method
for sector identification. The intended controller provides the desired power references to select the optimal switching sequences.
The switching orders follow the grid reference to drive the voltage source inverter (VSI), so the SAPF achieves good performances
while ensuring balanced overall supply currents, unity power factor, and reduced harmonic load currents. The proposed digital
implementation achieves a valuable compromise between fast dynamic response, minimum execution time, and reduced FPGA
resources, through a simple hardware design implementation. The entire system is developed and simulated using VHDL and VHDL-
AMS languages.